A static random-access memory (SRAM) cell employs six MOSFETs (6T topology) to store one bit of digital state without requiring dynamic refreshing. Two cross-coupled CMOS inverters form a bistable latch with two stable equilibrium states (Q=1/Q̄=0 or Q=0/Q̄=1). Access transistors connected to the Wordline (WL) selectively couple internal storage nodes to complementary Bitlines (BL and BL̄) for differential read sensing and write overwrite operations.