A phase-locked loop (PLL) is an electronic closed-loop control system that aligns the phase and frequency of a synthesized oscillator signal with an external reference clock. A phase-frequency detector (PFD) generates charge error pulses proportional to instantaneous phase differences, which a low-pass loop filter smooths into an analog control voltage V_ctrl. This voltage drives a Voltage-Controlled Oscillator (VCO), enabling dynamic frequency multiplication, clock de-skewing, and low-jitter distribution.