A complementary metal-oxide-semiconductor (CMOS) inverter combines a p-channel MOSFET pull-up network and an n-channel MOSFET pull-down network with interconnected gates and drains. Driving the input voltage HIGH (V_DD) activates the NMOS transistor to pull the output to ground while the PMOS cuts off; conversely, driving the input LOW activates the PMOS to pull the output to V_DD. Because one complementary switch is always in non-conduction in static steady-state, static power dissipation remains near zero.