Page Table — Physics Simulation

How It Works

A page table is an operating system kernel data structure that enables virtual memory virtualization by mapping virtual memory addresses into physical RAM page frames. The processor Memory Management Unit (MMU) extracts Virtual Page Numbers (VPN) to traverse multi-tiered page tables, resolving the Physical Frame Number (PFN). Translation Lookaside Buffers (TLBs) act as associative hardware caches for recently resolved addresses, bypassing memory hierarchy walks on cache hits.

Governing Equation

PA = (PFN ≪ OffsetBits) | Offset , AMAT = t_{TLB} + (1 - h_{TLB}) · t_{DRAM}