A digital NOT gate, or logic inverter, performs Boolean negation by asserting the logical complement of its input variable. When a logical HIGH voltage is applied to the input terminal, the output pulls down to logical LOW; conversely, a LOW input results in a HIGH output. In complementary MOS (CMOS) technology, a single pMOS pull-up transistor and a single nMOS pull-down transistor switch complementarily, consuming virtually zero static power during steady-state operations.